Substrates that include one or more layers of semiconductor material are used to form a wide variety of semiconductor structures and devices including, for example, integrated circuit (IC) devices (e.g., logic processors and memory devices) and discrete devices, such as radiation-emitting devices (e.g., light-emitting diodes (LEDs), resonant cavity light-emitting diodes (RCLEDs), vertical cavity surface emitting lasers (VCSELs)), and radiation-sensing devices (e.g., optical sensors). Such semiconductor devices are conventionally formed in a layer-by-layer manner (i.e., lithographically) on and/or in a surface of a semiconductor substrate.
Historically, a majority of such semiconductor substrates that have been used in the semiconductor device manufacturing industry have comprised thin discs or “wafers” of silicon material. Such wafers of silicon material are fabricated by first forming a large generally cylindrical silicon single crystal ingot and subsequently slicing the single crystal ingot perpendicularly to its longitudinal axis to form a plurality of silicon wafers. Such silicon wafers may have diameters as large as about thirty centimeters (30 cm) or more (about twelve inches (12 in) or more). Although silicon wafers generally have thicknesses of several hundred microns (e.g., about 700 microns) or more, only a very thin layer (e.g., less than about three hundred nanometers (300 nm)) of the semiconductor material on a major surface of the silicon wafer is generally used to form active devices on the silicon wafer. However, in some device applications, the majority of the silicon wafer thickness may be included in the electrical path-way of one or more device structures formed from the silicon wafer, such device structures being commonly referred to as “vertical” device structures.
So-called “engineered substrates” have been developed that include a relatively thin layer of semiconductor material (e.g., a layer having a thickness of less than about three hundred nanometers (300 nm)) disposed on a layer of dielectric material (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3)). Optionally, the layer of dielectric material may be relatively thin (e.g., too thin to enable handling by conventional semiconductor device manufacturing equipment), and the semiconductor material and the layer of dielectric material may be disposed on a relatively thicker host or base substrate to facilitate handling of the overall engineered substrate by manufacturing equipment. As a result, the base substrate is often referred to in the art as a “handle” or “handling” substrate. The base substrate may also comprise a semiconductor material other than silicon.
A wide variety of engineered substrates are known in the art and may include semiconductor materials such as, for example, silicon (Si), silicon carbide (SiC), germanium (Ge), III-V semiconductor materials, and II-VI semiconductor materials.
For example, an engineered substrate may include an epitaxial layer of III-V semiconductor material formed on a surface of a base substrate, such as, for example, aluminum oxide (Al2O3) (which may be referred to as “sapphire”). The epitaxial layer may be formed on the surface of the base substrate by a transfer process from a donor structure, for example, a donor substrate or donor ingot. The transfer from a donor structure may be desirable when the donor material is highly valuable or in scarce supply. Using such an engineered substrate, additional layers of material may be formed and processed (e.g., patterned) over the epitaxial layer of III-V semiconductor material to form one or more devices on the engineered substrate. However, the Coefficient of Thermal Expansion (CTE) mismatch (or difference) between the epitaxial layer and the base substrate comprising the engineered substrate, may influence the formation and processing of the additional layers of material. For example, if the CTE mismatch between the epitaxial layer and the base substrate is substantial, then the engineered substrate may be negatively impacted during the formation of additional layers of materials.
In an effort to address the issue of CTE mismatch between an epitaxial layer of GaN and the base substrate, it has been proposed to employ a molybdenum substrate in the formation of an engineered substrate that includes a layer of GaN on the substrate.